Table of Contents
Structural VHDLRASSP Education & FacilitationModule 11Version 2.01
RASSP Roadmap
Module Goals
Module Outline
Putting It All Together
Introduction
PPT Slide
Mechanisms for IncorporatingVHDL Design Objects
4-Bit Register as Running Example
General Steps to Incorporate VHDL Design Objects
Using Component Declarations and Local Bindings
Using Component Declarations and Configurations
Power of Configuration Declarations
Instantiation Statement
Generic Map
Component Binding Specifications
Binding Indication
Using Direct Instantiation
Rules for Actuals and Locals
Summary of Concepts of Structural VHDL
PPT Slide
Generate Statement
Generate StatementFOR-Scheme
FOR-Scheme Example
Generate StatementIF-Scheme
IF-Scheme Example
PPT Slide
Examples
Structural And-Or-Invert Gate Example(Entity)
Structural And-Or-Invert Gate Example(Architecture)
Structural AOI Gate Simulation Results
Structural 8 Bit Register ExampleSimple Generate Statement
Structural 8 Bit Register Simulation Results
Structural 8 Bit Shift Register Example(Entity)
Structural 8 Bit Shift Register Example(Architecture - Generate with If Scheme)
Structural 8 Bit Shift Register Simulation Results
Unsigned 8 Bit Multiplier Data Path (Entity)
Unsigned 8 Bit Multiplier Data Path (Architecture)
Unsigned 8 Bit Multiplier Data Path (Architecture)
Unsigned 8 Bit Multiplier Data Path Simulation Results
PPT Slide
Summary
References
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Author: Robert Klenke
Email: rhklenke@vcu.edu
Home Page: http://saturn.vcu.edu/~rhklenke
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