Slide 18 of 43
Notes:
The direct instantiation method was introduced in VHDL-93. It allows a VHDL design object to be plugged in directly to an architecture’s description by connecting local signals to its interface. This mechanism does not require the use of an idealized component to be declared, instantiated, and bound. Rather, a VHDL entity/architecture object may be inserted into an architecture description in one step.
