A Post-Doc and GRADUATE RESEARCH ASSISTANTSHIPS AVAILABLE FOR Spring 2018 or Fall 2018 
I am currently looking for a post-doc and multiple highly-motivated graduate students to perform research in the fields of real-time and embedded systems, compiler, computer architecture and security.
Applicants should have a M.S or B.S degree in Computer Science, Computer Engineering or a closely related discipline (or Ph.D. for Post-Doc applicants). Excellent programming skill in C/C++ or Java is a must. Research background or deep understanding in computer architecture, compiler, security, and/or real-time and embedded systems is highly preferred. Preference will be given to Ph.D. students who have had M.S research or relevant industrial experience and have strong analytic and problem-solving skills.
Those who are interested can contact Dr. Wei Zhang by wzhang4@vcu.edu or stop by my office if you are already at VCU.
GRADUATE STUDENTS CURRENTLY WORKING WITH ME
- Yijie Huangpu (Ph.D. student, B.S/M.S Dalian University of Technology)
- Hao Wen (Ph.D.student, B.S. Southeast Univ, M.S PeKing Univ)
- Xin Wang (Ph.D. student, B.S. Peking Univ)
Ph.D. STUDENTS GRADUATED
- Jun Yan (Ph.D. August 2009, M.S. Tianjin University, First Employment: MathWorks)
- Yu Sun (Ph.D. August 2010, B.S. Tsinghua Univ, M.S. Chinese Academy of Sciences First Employment: MathWorks)
- Yu Liu (Ph.D. August 2011, B.S/M.S Sichuan Univ, First Employment: Platform Computing, now IBM)
- Yiqiang Ding (Ph.D. December 2012, B.S./M.S Beijing University of Posts and Telecommunication, First Employment: Amazon)
- Lan Wu (Ph.D. Dec. 2013, B.S. University of Science and Technology of China, M.S. NCICT, First Employment: Microsoft)
M.S. STUDENTS GRADUATED
- Matthew Loach, Studies of Performance and Time Predictability of Cache Locking (M.S. 2013, First Employment: Intel)
- Anil Kumar Reddy Devadi, Evaluating cache vulnerability to transient errors for uniprocessors and multiprocessors (M.S. 2009, First Employment: Intel)
- Mutaz Abdel-Latif Barakat Al-Tarawneh, Worst-case performance analysis of low-power instruction caches (M.S. 2008, SIUC Ph.D. program)
- Prabhu Annabathula, Clustering with tree based architecture: protocol to extend life time of sensor networks (M.S. 2007, First Employment: Motorola)
- Abhishek Pillai, Improving performance for dual instruction execution by selective instruction duplication (M.S. 2006, First Employment: Intel)
- Mallik Kandala, Improving the reliability of registers by enhancing the conventional conservative based scheme (M.S. 2005, SIUC Ph.D. program)
- Bramha Allu, Compiler-directed leakage energy reduction for large on-chip array structures (M.S. 2005, First Employment: SAP FICO Consultant)
UNDERGRADUATE STUDENTS WHO HAVE WORKED WITH ME IN REU (RESEARCH EXPERIENCE FOR UNDERGRADUATE) PROJECTS
- Morgan Stuart, Visualization of Performance-Oriented Multicore Programming, Spring 2013
- David Koslow, Hardware/Software Co-design of Mpeg Decoding, Spring 2012
- Mutaz Abdel-Latif Barakat Al-Tarawneh, Worst-case performance analysis of low-power instruction caches (M.S. 2008, SIUC Ph.D. program)
- Karl Lee Daman, Time Predictability of Out-of-Order Execution, Summer 2011
- Morgan Simmons Stuart, Performance Implication of Unified Level 1 Cache, Summer 2011
- Jack Vo, Modeling NUCA Caches in Simplescalar, Spring 2011
- Matthew Loach, Enhancing Cache Locking for Time Predictability, Summer 2009
- Tyler Ferro. Impact of Cache Configuration on the Energy Dissipation of Jikes RVM (supported by NSF REU Supplement grant), Fall 2008
- Brandon Dwiel, Energy Evaluation of Dynamic Compiler Optimizations in IBM Jikes RVM (supported by NSF REU Supplement grant), Summer 2008
- Scot Shelton, WCET-oriented Data Prefetching (supported by NSF REU Supplement grant), Summer 2008
- Joseph Lenox, Evaluating the Impact of Data Prefetching on Time Predictability (supported by NSF REU Supplement grant), Summer 2008
- Scot Shelton, Parallelizing Single-Threaded Programs to Boost Performance on Hybrid Multi-Core Processors (supported by NSF REU Supplement grant), Summer 2007
- Brian D. Jordan, Donald Owens, Area and Performance Tradeoffs in the Design of Hybrid Multi-Core Chips (supported by NSF REU Supplement grant), Fall 2007