Wei Zhang, Ph.D.

Professor and Director of Computer Engineering
Electrical and Computer Engineering
VCU School of Engineering

Selected Refereed Journal Articles

  1. Y. Huangfu and W. Zhang. PEG-C: Performance Enhancement Guaranteed Cache for Hard Real-Time Systems. IEEE Embedded Systems Letters (ESL), Vol. PP, Issue 99, Jan 2nd, 2014.
  2. Y. Liu and W. Zhang. Static Worst-Case Lifetime Estimation of Wireless Sensor Networks: A Case Study on VigilNet. Journal of Systems Architecture, Volume 59, Issue 4-5, pages 224-233, April-May, 2013.
  3. Y. Ding and W. Zhang. Architectural Time-predictability Factor (ATF): A Metric to Evaluate Time Predictability of Processors. ACM Special Interest Group on Embedded System (SIGBED) Review, Nov, 2012.
  4. L. Wu, W. Zhang. A Model Checking Based Approach to Bounding Worst-case Execution Time for Multicore Processors. ACM Transactions on Embedded Computer Systems (TECS), Vol. 11, No. S2, Article 56, August, 2012.
  5. Y. Ding and W. Zhang. Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time. IEEE Transactions on Computers, Feb 2010.
  6. Y. Sun and W. Zhang. Improving java performance and energy dissipation through efficient code caching. International Journal of Design Automation for Embedded Systems, Vol. 3, No. 3, pp. 179-192, June 2009.
  7. W. Zhang. Computing and Minimizing Cache Vulnerability to Transient Errors. IEEE Design &Test of Computers, Vol. 26, No. 2, pp. 44-51, March/April 2009.
  8. J. Yan, W. Zhang. Analyzing the worst-case execution time for instruction caches with prefetching. ACM Transactions on Embedded Computer Systems (TECS), Vol. 8, No. 1, Article 7, December 2008.
  9. J. Yan, W. Zhang. A time-predictable VLIW processor and its compiler support. In the Journal of Real-Time Systems, Vol. 38, No. 1, pp. 67 – 84, Jan. 2008.
  10. J. Yan, W. Zhang. Exploiting virtual registers to reduce pressure on real registers. In ACM Transactions on Architecture and Code Optimization (TACO), Vol. 4, No. 4, pp. 1 – 18, Jan. 2008.
  11. W. Zhang, B. Allu. Reducing branch predictor leakage energy by exploiting loops. In ACM Transactions on Embedded Computer Systems (TECS), Vol. 6, No. 2, pp. 33 – 50, May 2007.
  12. B. Allu, W. Zhang. Reducing iTLB energy dissipation through compiler-directed resizing. Published in Journal of Low Power Electronics, Vol. 2, No. 2, pp. 140-147, August 2006.
  13. W. Zhang. Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy. Published in Journal of Embedded Computing (JEC): Special Issue on Embedded Processors and Systems: Architectural Issues and Solutions for Emerging Applications, Vol. 2, No. 1, pp. 35-48, 2006.
  14. W. Zhang, Y.-F. Tsai, D. Duarte, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Reducing dynamic and leakage energy in VLIW architectures. Published in ACM Transactions on Embedded Computer Systems (TECS), Vol. 5, No. 1, pp. 1-28, February 2006.
  15. W. Zhang. Replication cache: A small fully associative cache to improve data cache reliability. Published in IEEE Transactions on Computers, Vol. 54, No. 12, pp. 1547-1555, Dec. 2005.
  16. W. Zhang, Y-F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and V. De. Leakage-aware compilation for VLIW architectures. Published in IEE Proceedings-Computers and Digital Techniques, Vol. 152, No. 2, pp. 251-261, March 2005.
  17. W. Zhang. Exploiting loop behavior for data cache leakage reduction. Published in Journal of Embedded Computing (JEC): Special Issue on Data Cache Analysis and Optimizations for Embedded Systems. Vol. 1, No. 4, pp. 501-508, IOS Press, 2005.
  18. W. Zhang, M. Kandemir, M. Karakoy, and G. Chen. Reducing data cache leakage energy using a compiler-based approach. Published in ACM Transactions on Embedded Computer Systems (TECS), Vol. 04, Issue 03, pp. 652 - 678, August, 2005.
  19. B. Allu, W. Zhang. Exploiting the replication cache to improve performance for multiple-issue microprocessors. Published in ACM SIGARCH Computer Architecture News, Vol. 33, No. 3, pp. 63-71, June 2005.
  20. W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Reducing instruction cache energy consumption using a compiler-based strategy. Published in ACM Transactions on Architecture and Code Optimization (TACO), page 3-33, Vol. 1, Issue 1, March, 2004.

Selected Refereed Conference Proceedings (Published or Accepted for Publication)

  1. Y. Huangfu and W. Zhang. Real-Time GPU Computing: Cache or No Cache? In Proc. of 18th IEEE International Symposium on Object Oriented Real-Time Distributed Computing (ISORC), April, 2015.
  2. Y. Huangfu and W. Zhang. Hardware-Based Performance Enhancement Guaranteed Caches In Proc. of 18th IEEE International Symposium on Object Oriented Real-Time Distributed Computing (ISORC), April, 2015.
  3. H. Wen and W. Zhang. Exploring Shared Memory and Cache to Improve GPU Performance and Energy Efficiency. In Proc. of the International Symposium on Quality Electronic Design (ISQED), March, 2015.
  4. L. Wu and W. Zhang. Cache-Aware SPM Allocation Algorithms for Hybrid SPM-Cache Architectures. In Proc. of the International Symposium on Quality Electronic Design (ISQED), March, 2015.
  5. Y. Ding and W. Zhang. WCET Analysis of Static NUCA Caches. In Proc. of the 33rd IEEE International Performance Computing and Communications Conference (IPCCC), Dec, 2014.
  6. Y. Huangfu and W. Zhang. Worst-Case Performance Guaranteed Data Cache (poster paper). In Proc. of the 33rd IEEE International Performance Computing and Communications Conference (IPCCC), Dec, 2014.
  7. H. Wen and W. Zhang. Reducing Cache Leakage Energy for Hybrid SPM-Cache Architectures. In Proc. of the International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES), Oct. 2014.
  8. W. Zhang and L. Wu. Exploiting Hybrid SPM-Cache Architectures to Reduce Energy Consumption for Embedded Computing. In Proc. of the 16th IEEE International Conference on High Performance Computing and Communications (HPCC), August, 2014.
  9. M. Loach and W. Zhang. Performance Implication of Multicore Cache Locking on General-Purpose Processors. In Proc. of the 16th IEEE International Conference on High Performance Computing and Communications (HPCC), August, 2014.
  10. L. Wu, Y. Ding, and W. Zhang. Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches. In Proc. of the 11th IEEE International Conference on Embedded Software and Systems (ICESS), August, 2014 (acceptance rate 24.7%).
  11. Y. Ding and W. Zhang. Bounding the Worst-Case Execution Time of Static NUCA Caches. In the Proceeding of the Work-in-Progress (WiP) session of the 11th IEEE International Conference on Embedded Software and Systems (ICESS), August, 2014.
  12. J. Yan and W. Zhang. Deterministic L2 Cache Design and Its WCET Analysis. In the Proceeding of the Work-in-Progress (WiP) session of the 11th IEEE International Conference on Embedded Software and Systems (ICESS), August, 2014.
  13. Y. Ding and W. Zhang. Hop-based Priority Scheduling to Improve Worst-Case Inter-Core Communication Latency. In Proc. of the 12th IEEE International Conference on Embedded and Ubiquitous Computing (EUC), August 2014.
  14. Y. Sun and W. Zhang. Improve Energy Efficiency with Dynamic Compiler-Directed Function Unit Power Control (poster paper). In Proc. of the 12th IEEE International Conference on Embedded and Ubiquitous Computing (EUC), August 2014.
  15. L. Wu and W. Zhang. Cache-Aware SPM Allocation to Reduce Energy Consumption for Hybrid SPM-Cache Architectures. Work-in-Progress (WiP) session, ACM/IEEE Design Automation Conference (DAC), June 2014.
  16. Y. Huangfu and W. Zhang. A Real-Time Instruction Cache with High Average-Case and Guaranteed Worst-Case Performance. In Proc. of the 17th IEEE International Symposium on Object Oriented Real-Time Distributed Computing (ISORC), June, 2014.
  17. Y. Huangfu and W. Zhang. Compiler-Directed Leakage Energy Reduction for Instruction Scratch-Pad Memories. To Appear In Proc. of the International Symposium on Quality Electronic Design (ISQED), March, 2014.
  18. L. Wu and W. Zhang. Reducing Worst-Case Execution Time of Hybrid SPM-Caches. In Proc. of the 32nd IEEE International Performance Computing and Communications Conference (IPCCC), Dec, 2013. (Acceptance rate: 27.8%)
  19. W. Zhang. Defend GPUs Against DoS Attacks (poster paper). In Proc. of the 32nd IEEE International Performance Computing and Communications Conference (IPCCC), Dec, 2013.
  20. Y. Huangfu and W. Zhang. Compiler-Based Approach to Reducing Leakage Energy of Instruction Scratch-Pad Memories (poster paper). In Proc. of the 31st IEEE International Conference on Computer Design (ICCD), Oct, 2013.
  21. W. Zhang and Y. Ding. Hybrid SPM-Cache Architectures to Achieve High Time Predictability and Performance. In Proc. of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), June, 2013. (Acceptance rate: 19.2%)
  22. Y. Ding and W. Zhang. Standard Deviation of CPI: A New Metric to Evaluate Architectural Time Predictability. In Proc. of the 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (poster paper), June, 2013.
  23. Y. Ding and W. Zhang. On the Interactions between Real-Time Scheduling and Inter-thread Cache Interferences for Multicore Processors. In Proc. of the International Symposium on Quality Electronic Design (ISQED), March, 2013.
  24. Y. Liu and W. Zhang. Exploiting Multi-Level Scratchpad Memories for Time-Predictable Multicore Computing. In Proc. of the 30th IEEE International Conference on Computer Design (ICCD), Oct, 2012. (Acceptance rate: 25%)
  25. Y. Ding and W. Zhang. Multicore-Aware Code Positioning to Improve Worst-Case Performance. In Proc. of the 14th IEEE International Symposium on object/Component/Service-oriented Real-time Distributed Computing (ISORC), March 2011.
  26. Y. Liu and W. Zhang. Stack Distance Based Worst-Case Instruction Cache Performance Analysis. In Proc. of the Real-Time Systems (RTS) Track of the 26th Symposium on Applied Computing (SAC), March 2011. (Acceptance rate: 30%)
  27. Y. Liu and W. Zhang. Exploiting Time-Predictable Two-Level Scratchpad Memory for Real-Time Systems (poster paper). In Proc. of the Embedded Systems Track (EMBS) of the 26th Symposium on Applied Computing (SAC), March 2011.
  28. J. Yan and W. Zhang. Time-Predictable L2 Cache Design for High-Performance Real-Time Systems. In Proc. of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2010), August 2010.
  29. Y. Liu, W. Zhang, and K. Akkaya. Static Worst-Case Energy and Lifetime Estimation of Wireless Sensor Networks. In Proc. of the 28th International Performance Computing and Communications Conference (IPCCC), December 2009. (Acceptance rate: 29.7%)
  30. W. Zhang and J. Yan. Accurately Estimating Worst-Case Execution Time for Multi-Core Processors with Shared Instruction Caches. In Proc. of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2009), August 2009. (Acceptance rate: 31%)
  31. Y. Sun and W. Zhang. Exploiting Multi-Core Processors to Improve Time Predictability for Real-time Java Computing. In Proc. of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2009), August 2009. (Acceptance rate: 31%)
  32. Y. Liu and W. Zhang. Exploiting Stack Distance to Estimate Worst-Case Data Cache Performance. In the Proc. of the Real-Time Systems track of the 24th Annual ACM Symposium on Applied Computing, March 2009.
  33. Y. Sun and W. Zhang. Adaptive drowsy cache control for java applications. In the Proc. of the 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), December 2008.
  34. Y. Sun and W. Zhang. Efficient code caching to improve performance and energy consumption for Java applications. In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’08), Oct 2008.
  35. Y. Sun and W. Zhang. On the energy efficiency of Java virtual machine. In Proc. of the 2008 International Conference on Embedded Systems and Applications, July 2008.
  36. J. Yan, W. Zhang. WCET analysis for multi-core processors with shared instruction caches. In Proc. of 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’08), April 2008. (Acceptance rate: 25%)
  37. J. Yan, W. Zhang. WCET analysis of multi-core processors. In Proc. of the Work-in-Progress (WIP) session of The 28th IEEE Real-Time Systems Symposium, December 2007.
  38. J. Yan, W. Zhang. Virtual registers: reducing register pressure without enlarging the register file. In Proc. of the 2007 International Conference on High Performance Embedded Architectures & Compilers, page 57-70, January 2007 (Acceptance rate: 29%).
  39. J. Yan, W. Zhang. WCET Analysis of time-predictable VLIW processors. In Proc. of the Work-in-Progress (WIP) session of The 27th IEEE Real-Time Systems Symposium, pages 85-88, December 2006.
  40. W. Zhang. Computing cache vulnerability to transient errors and its implication. In Proc. of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05), page 427-435, Oct. 2005.
  41. J. Yan and W. Zhang. Compiler-guided register reliability improvement against soft errors. In Proc. of the ACM Conference on Embedded Software (EMSOFT), pages 203-209, Sep. 2005. (Acceptance rate: 28%)
  42. B. Allu, W. Zhang. Loop-based iTLB resizing for energy reduction. In Proc. of the second IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (PAC'2), pages 153-159, Sep, 2005.
  43. J. Yan, W. Zhang. Enhancing register file reliability through compiler-based approaches. In Proc. of the second IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (PAC'2), pages 170-177, Sep, 2005.
  44. W. Zhang. Replica victim caching to improve reliability of in-cache replication. In Proc. of the 9th Asia-Pacific Computer Systems Architecture Conference (ACSAC’04), pages 2-15, Sep, 2004. (Acceptance rate: 26.1%)
  45. B. Allu and W. Zhang. Static next sub-bank prediction for drowsy instruction cache. In Proc. of the International Conference on Compiler, Architecture, and Synthesis for Embedded Systems (CASES’04), pages 124-131, Sep, 2004. (Accepted 31 out of 102 submissions, acceptance rate: 30.4%)
  46. W. Zhang and B. Allu. Loop-based leakage control for branch predictors. In Proc. of the International Conference on Compiler, Architecture, and Synthesis for Embedded Systems (CASES’04), pages 149-155, Sep, 2004. (Accepted 31 out of 102 submissions, acceptance rate: 30.4%)
  47. W. Zhang. Enhancing data cache reliability by the addition of a small fully-associative replication cache. In Proc. of the 18th Annual ACM International Conference on Supercomputing (ICS’04), pages 12-19, June 2004. (Accepted 25 out of 162 submissions, acceptance rate: 22%)
  48. W. Zhang. Compiler-directed data cache leakage reduction. In Proc. of the IEEE Computer Society Symposium on VLSI (ISVLSI’04), pages 305-306, Feb 2004.
  49. W. Zhang, M. Kandemir, A. Sivasubramaniam, and M. J. Irwin. Performance, energy, and reliability tradeoffs in replicating hot cache lines. In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'03), pages 309-317, San Jose, CA, October 30-November 1, 2003. (Accepted 31 out of 162 submissions, acceptance rate: 19%)
  50. W. Zhang, S. Gurumurthi. M. Kandemir, A. Sivasubramaniam. ICR: In-cache replication for enhancing data cache reliability. In Proc. of the International Conference on Dependable Systems and Networks (DSN’2003), pages 291 – 300, June 2003.
  51. W. Zhang, G. Chen, M. Kandemir, and M. Karakoy. Interprocedural optimizations for improving data cache performance of array-intensive embedded applications. In Proc. of the 40th Design Automation Conference (DAC’03), pages 887 – 892, Anaheim, CA, June 2003. (Acceptance rate 24%)
  52. W. Zhang, M. Karakoy, M. Kandemir, and G. Chen. A compiler approach for reducing data cache energy. In Proc. of the 17th Annual ACM International Conference on Supercomputing (ICS'03), pages 76 – 85, San Francisco, CA, June 23-26, 2003. (Acceptance rate 21.05%)
  53. M. Kandemir, G. Chen, W. Zhang, and I. Kolcu. Data space oriented scheduling in embedded systems. In Proc. of the 6th Design Automation and Test in Europe Conference (DATE'03), Munich, Germany, March, 2003.
  54. H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, and W. Zhang. Masking the energy behavior of DES encryption. In Proc. of the 6th Design Automation and Test in Europe Conference (DATE'03), Munich, Germany, March, 2003.
  55. M. Kandemir, W. Zhang, and I. Kolcu. Implementation and evaluation of an on-demand parameter-passing strategy for reducing energy. In Proc. the 6th Design Automation and Test in Europe Conference (DATE'03), Munich, Germany, March, 2003.
  56. W. Zhang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and V. De. Compiler support for reducing leakage energy consumption. In Proc. of the 6th Design Automation and Test in Europe Conference (DATE'03), Munich, Germany, March, 2003.
  57. M. Kandemir, W. Zhang, and M. Karakoy. Runtime code parallelization for on-chip multiprocessors. In Proc. of the 6th Design Automation and Test in Europe Conference (DATE'03), Munich, Germany, March, 2003.
  58. W. Zhang, J. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Compiler-directed instruction cache leakage optimization. In Proc. of the 35th Annual International Symposium on Microarchitecture (MICRO’35), pages 208 – 218, Istanbul, Turkey, November 2002. (Accepted 36 out of 150 submissions, acceptance rate: 24%)
  59. W. Zhang, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte and Y. Tsai. Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. In Proc. of the 34th Annual International Symposium on Microarchitecture (MICRO’34), pages 102 – 113, Austin, December 2001. (Acceptance rate: 20%)
Wei Zhang, Ph.D.
Professor and Director of Computer Engineering
Department of Electrical and Computer Engineering
Phone: (804) 827-2631 (0)
Fax: (804) 827-0006
Email: wzhang4@vcu.edu
Faculty Page: http://electrical-and-computer.egr.vcu.edu/faculty/zhang/
Virginia Commonwealth University
School of Engineering
Department of Electrical and Computer Engineering
West Hall, Room 238
601 West Main Street
P.O. Box 843072
Richmond, Virginia 23284-3072
Last Updated: 9/12/2014