Slide 34 of 65
Notes:
To review, bus resolution functions are used to determine the value assigned to a signal connected to two or more active drivers. The input to the bus resolution function is a VHDL simulator-generated array of the active drivers to the signal in question. The user-defined bus resolution function can use this array of drivers to determine what value the signal will have at all ports where it will be read. Examples include wired-or and wired-and functions, but the user may define much more sophisticated abstract functions based on user-defined status fields, etc.
Note that Bus Resolution Functions are ordinary functions except for the fact that they are called implicitly by the simulator rather than explicitly by the VHDL programmer. Also note that the input is an array of signals each of which is the same type as the returned signal.
Each process that makes an assignment to a particular signal is a driver of that signal. Note that concurrent signal assignment statements are equivalent to one line processes; thus, no two concurrent signal assignment statements may make assignments to the same signal without a bus resolution function.
