Slide 9 of 53
Notes:
VHDL provides the alias construct to enhance readability in VHDL descriptions. Aliases are available in two varieties:
1. Object aliases rename objects
a. constant
b. signal
c. variable
d. file
2. Non-object aliases rename items that are not objects
a. function names
b. literals
c. type names
d. attribute names
[Bhasker95]
