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Notes:
VHDL packages are collections of reusable declarations and descriptions of VHDL types, subtypes, subprograms, aliases, constants, attributes, components, etc.
The declaration section of a package contains declaration statement for all the elements in the package. For several elements (e.g. TYPE definitions), the declaration is all that is needed. For some elements, however (e.g. subprograms), a functional description is also needed. This additional information is placed in the body section of the package.
