Slide 12 of 65
Notes:
Alternatively, the Sum and Carry functions of a full-bit adder can each be represented in VHDL with a single sequential assignment statement:
Carry <= A AND B OR A AND Cin OR B AND Cin;
We can represent these two functions each in separate process statements (but both in the same architecture), as shown above, or together in the same process statement.
In the example shown here, the sensitivity lists contain all the signals on the right-hand side of the signal assignment statements. This allows any change on any of the right-hand-side signals to cause an evaluation of the VHDL statements to determine a potential new value for the output signals.
