VHDL Design Example

Slide 22 of 93

Notes:

In the first stage of the design process, a high level behavior of the adder is considered. This level uses abstract constructs (such as the IF-THEN-ELSE statement) to make the model more readable and understandable.

Simulation of the adder at this level shows correct understanding of the problem specifications of the adder. VHDL code for this adder will be shown later.