Schematic Driven Cell Layout Using ADK

In this lab, you will use both DA and ICStation in cooperation to design a CMOS NOR gate.

1.1 Move into the directory you created for this class, create a directory for lab 5, and move into it. Then start DA:

>> cd egre429
>> mkdir lab5
>> cd lab5
>> adk_da &

1.2 Open a sheet called nor2. Use your knowledge of DA to create a schematic of a CMOS NOR gate like the one below:

1.3 Check and save the sheet and exit DA.
 

2.1 Create an Accusim viewpoint and open Accusim on the nor2 design:

>> asim_prep nor2
>> accusim nor2/accusim &

2.2 Set up a transient analysis for 200 ns, trace the A, B, and Y signals, load the AMI 0.5 model library and force a pulse with pulse width 100N and period 200N (don't forget to set it to 0V and 5V!) on signal A and a pulse with pulse width 40N and period 80N on signal B. Run the simulation and you should get a chart like the one below:

2.3 Exit Accusim without saving.
 

 
Here we are going to use one of the advanced features of ICStation within the Mentor environment to have the schematic of the NOR gate help generate the layout. This function is called schematic driven layout (SDL). The SDL functions within the Mentor environment (along with the ADK design kit support) will help us to automatically create the transistors via a device generator, and to track the wiring of the cell so that it matches the schematic we originally created. In the end, we can check the layout to see if in fact, it still matches the schematic. This function is called LVS - Layout Vs. Schematic.

3.1 Prepare the schematic of the nor2 gate you created for use in SDL:

>> adk_dve nor2

You will see a number of messages from the Mentor DVE tool. This process should complete without any errors or warnings.

3.2 Start ICStation in your lab5 directory:

>> adk_ic &

3.3 In the Session palette, under Cell, click on Create. In the Create Cell dialog box that comes up, enter a cell name of nor2, click the With Connectivity button and when the dialog box changes, leave the Logic Source Type set to EDDM. Click the Navigator... button next to the EDDM Schematic Viewpoint box and select the sdl viewpoint under your nor2 component. Set the Process box to point to the $ADK/technology/ic/ami05 process file and the Rules File box to point to the $ADK/technology/ic/ami05.rules file as you did for the full custom design. The result should be a dialog box like the one below:

Click OK and a new IC window should appear.

3.4 Use the Context->Set Cell Config->Connectivity Editing menu item to put ICStation into the connectivity editing mode. This is VERY important when using SDL as it causes ICStation to warn you when an edit operation (such as adding a path) you are making on the current cell will merge 2 nets in the cell. Merging nets in the cell that should not be connected will cause the database to be corrupted such that extraction and LVS will no longer work correctly.

3.5 In the IC Palettes palette, click on DLA Layout (or ADK_Edit). In the DLA Layout (or ADK_EDIT) palette, click Logic->Open. The schematic of your nor2 gate should appear as below:

3.6 Create the power (VDD) and ground (GND) rails for the nor2 cell by making the IC window active, placing the cursor in the IC window and typing pr().  You should see the rails appear with N_Well and P_Well above and below them in the proper spot. Note that the pr() command is just a macro that has been provided for you to make layout easier. This macro places Metal1 in the proper places for VDD and GND, makes them ports with those names, and places the N_Well and P_Well. You can move or resize the resulting structures to match any cell width or height you desire. If you do not use this macro, it is helpful to at least create the VDD and GND rails and make them ports before proceeding onto the next step so that the proper transistor connections to them are shown when the devices are created.
 

Schematic driven layout has two major advantages, first, as we will see, it keeps track of the wiring of the cell and helps you make sure that it matches the schematic. Second, it allows us to use the automatic device generators built into ICStation to generate the transistors with the proper sizing as specified in the schematic.

There are two ways to have the devices automatically generated and placed on the schematic. The first way is to simply click on the AutoInst button under the DLA Layout palette. This will place all of the transistors in the schematic in the device for you and will merge devices together that can share common diffusion areas. This method of placing the transistors is often the fastest way to do it. However, for this exercise, we will use a more manual method that is often handy to make a better placement of devices than the automatic placement can.

4.1 make the schematic window active and select the bottom pmos device. Make the IC window active and in the DLA Layout palette, click on Place > Inst. A transistor labeled mos() will be created and will follow the cursor in the IC window. Place this transistor even with the left edge of the existing N_Well and immediately below it. Make the schematic active again and select the top pmos device. Create it in the IC window as you did the other device and place it to the right, but not touching, the other pmos device. Place the rightmost nmos device in the schematic into the IC window immediately below the pmos device it is connected to (you'll see that when you create it), and place the leftmost nmos device to the right, under the pmos device it is connected to. The result should be a layout like the one below:

Note the yellow lines, called overflows, that show you the connections on the transistors that need to be made. Also notice that some of the connections would be easier if some of the transistors were flipped.

4.2 Click on the edge of the left pmos device until the message at the bottom of the window says that "1 device ... is selected" Then you know you have the entire device (i.e. the transistor) selected. Click the Flip H button in the DLA Layout palette. Unselect all (hit F2).

4.3 Click on the right pin of the left pmos device to select it and you should get a message "Pin "s" on device "mos" ... " at the bottom of the ICStation window. Select the left pin of the right pmos device and you will get a message "2 pins selected". Click on the DEdit > button in the DLA Layout palette and a Device Edit sub-palette should appear. Select the Mos : Join item in the dialog box and place the resulting, joined pmos devices back where they should be. The result should be a layout like this now:

4.4 Select the nmos devices and flip them so that their common pins are adjacent and join them as well. Now move the devices around so that they lineup as well as possible and route Poly of width 2 between the connected gates.

4.5 Stretch the VDD and GND rails and the P_Well and N_Well to the edge of the devices so that everything lines up.

4.5 Route Metal1 from the pmos device to VDD and Metal1 from the nmos to GND as indicated by the overflows. Note that the overflows do go away when this routing is done. The result should be a layout like this:

 

5.1 Setup the port style by using the Setup->SDL item from the pull down menus. When the Setup SDL dialog box appears, click on the SDL Port Styles item in the Setup Values box and click the Setup... button. Click the Process Port button in the resulting Set Active Port Style dialog box and select the default (width=4) item in the Select a Port Style box. Click OK in both boxes.

5.2 Bring up the schematic window and select the A port. Make the IC window active and click the Port button in the DLA Layout palette. Place the resulting port at location 2,50. Do the same for the B port and place it at 15,50. Finally, place the Y port at 28,50. Notice that the overflows now connect the ports with the proper connections on the devices.

5.3 Add a Metal1 path of width 4 to from the pmos device, under the Y port, to the nmos device. Add a 2x2 Via at 29,51. Finally, add a Metal2 shape under the Y port from 28,50 to 32,54. This last step is very important! The ports are only defined in the Metal2.port layer, which is a dummy layer. Although it looks like Metal2, Metal2.port will not result in a real Metal 2 layer being deposited. You could always leave the Metal2 off of the cell as long as you made sure that you wired all the way across the port at the next level up in the hierarchy, but its probably best to go ahead and add the Metal2 layer in the cell, just to be sure (note that overlapping of the same layer is OK).

5.4 Use Poly, Metal1, Contact_to_poly, Metal2, and Via to route from the A and B ports to the poly gate lines. Also use Metal1 to connect the remaining pmos device to GND as shown by the overflows. The result might look something like this:

5.5 Now is a good time to do a DRC check, so click Top in the DLA Layout palette and go to the ICRules palette. Run a DRC check and you will find some errors in regards to the connections to the A and B ports. Correcting these will probably changing the routing of the poly connections for the gates connected to the B port. Once you fix the errors, you might wind up with something like this:

5.6 Now, when you do a DRC check, you should only get two errors, one for the missing N_Well contact and one for the missing P_Well (or substrate) contact. You can add those by hand as you did in the full custom design, or you can use the nwc() macro (for N well contact) and pwc() macro (for P well contact). The result should pass DRC and look something like this:

Note that some overflows still exist in the cell, but that appears to be a bug.

5.7 Don't forget to add shapes of fp1 and METAL1_BLKG with aspect set to both to the outline of your cell. Your cell is now complete, so use the File->Cell->Save Cell menu item to save it.
 

Here you will use LVS (layout vs. schematic) to be sure that your cell is wired correctly.

6.1 Go back to the IC Palettes palette and click on ICtrace (M). In the ICtrace (M) menu, click on LVS. You will get an LVS (Mask) dialog box. Under the Source Name box, click the Navigator... button and select the sdl viewpoint of the nor2 gate (it should appear right away in the navigator window). Click on the Setup LVS... button and set the Recognize Gates item to NO in the Setup LVS dialog box that comes up. Click OK in that dialog box and OK in the LVS (Mask) dialog box. A number of messages will flash by at the bottom of the ICStation window with "Mask results database loaded" as the last one.

6.2 To view the LVS results, select the Report item from the ICtrace (M) palette and select the LVS item from the popup menu that appears. The result should be a report window with the infamous "smiley face" as shown below:

6.3 Close the LVS report window.

6.4 At this time, if you'd like to clean up your cell, you can select the overflows that still remain and delete them - assuming that you've verified with LVS that the connections have in fact been made. If you do this you'll have to use the File->Cell->Reserve menu item to be able to edit the cell again and be sure to use the File->Cell->Save Cell menu item to resave your cell when you are done.
 

7.1 Click on Back in the ICtrace (M) palette to go back to the IC Palettes palette. Go to the ICextract (M) palette and click on Lumped. Click Yes on the Netlist item and enter nor2.sp for the Netlist name and enter GND for the Ground name. Click OK.

7.2 You can now exit ICStation.
 

8.1 Fix the nor2.sp file for use with MachTA:

>> cell_sim_prep nor2

8.2 Start MachTA on the fixed nor2 Spice file:
 

>> mta -t $ADK/technology/mta/ami05 mta_nor2.sp

8.3 Enter the following commands in the MachTA command window:

> plot v(a)
> plot v(b)
> plot v(y)
> h a
> h b
> run 10 ns
> l a
> l b
> run 10 ns
> h a
> run 10 ns
> l a
> run 10 ns
> h b
> run 10 ns
> l b
> run 10 ns

8.4 Open the Simwave window. The result should look like this:

8.5 Exit the Simwave window and MachTA.